Semiconductor package having isolated tape which include conductor circuit patterns

专利摘要:
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, wherein dummy bars formed between a die pad and inner leads are provided to prevent problems that may be caused by an increase in the density of inner leads. a plurality of conductor circuit patterns, and inner lead attachment grooves and bonding wire attachment grooves each exposing the conductor circuit patterns, the conductor circuit being exposed to the inner lead attachment grooves. The patterns are formed with conductive adhesive means, and the conductive circuit patterns exposed to the bonding wire attachment grooves include an insulating tape having a conductive plating layer formed thereon, the insulating tape being attached from the dummy bars across the inner leads, and the conductive adhesive. The inner lead is attached to the means, and a bonding wire connected to the bonding pad is attached to the conductive plating layer. It provides a semiconductor package characterized in that.
公开号:KR20030000816A
申请号:KR1020010036957
申请日:2001-06-27
公开日:2003-01-06
发明作者:김태형
申请人:삼성전자 주식회사；
IPC主号:

专利说明:

Semiconductor package having isolated tape which include conductor circuit patterns}
[26] BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, and more particularly to forming dummy bars between a die pad and internal leads, and further comprising an insulating tape including conductor circuit patterns, internal lead attachment grooves, and bonding wire attachment grooves. A semiconductor package configured to be attached from dummy bars to internal leads.
[27] As the performance of semiconductor packages increases, the number of leads of semiconductor packages increases with the increase of functions of semiconductor packages, and in the case of semiconductor packages having the same function or the same number of leads as the conventional semiconductor packages, the size thereof becomes smaller. Is showing. Increasing the number of leads and miniaturization of the semiconductor package has caused a problem of increased density in the inner leads. To solve this problem, the inner leads are processed finer to reduce the size of the inner leads or the die pad and the inner leads. It was necessary to increase the spacing between them and increase the length of the bonding wire by the enlarged spacing. However, the micromachining of the inner leads is very difficult to apply to universal manufacturing methods for mass production such as, for example, the stamping method, and the finer inner leads may be inadequate due to inadvertence during the manufacturing process. quality defects such as inner lead bent, etc., on the other hand, increasing the distance between the die pad and the inner leads not only leads to an increase in the manufacturing cost by increasing the use of expensive bonding wires, but also the bonding wires. Due to the increased length of the wire, quality problems such as wire sagging and wire sweeping could occur.
[28] 1A to 1C are diagrams illustrating an example of a semiconductor package according to the related art, and FIG. 1A is a perspective view showing an appearance of a semiconductor package, and FIGS. 1B and 1C are plan and cross-sectional views showing an inside view of a semiconductor package. As can be seen from these figures, when the density of the inner leads 40 is not so high, the inner leads 40 are not finely processed and the die pad 60 and the inner leads 40 are not finely processed. Although there is no big problem in accommodating the inner leads 40 and setting the size of the semiconductor package 200 without increasing the spacing, if the density of the inner leads 40 is further increased, the increased inner leads 40 are increased. In order to reduce the density of the inner cores 40, the inner leads 40 may be further processed to reduce the size of the inner leads 40, or to increase the distance between the die pad 60 and the inner leads 40. Since the length of the bonding wire 160 needs to be increased by the enlarged interval, the micromachining problem of the inner leads 40 as described above, a quality problem such as internal lead venting, wire sagging, and wire sweeping, and Expensive Bonding Y The manufacturing cost increases due to problems such as increase in the amount of 160, can be generated.
[29] Accordingly, an object of the present invention is to provide a semiconductor package capable of miniaturizing and polyfining a semiconductor package by preventing internal processing of the internal leads and increasing the density of the internal leads without increasing the length of the bonding wire.
[1] Figure 1a is a perspective view showing an example of a semiconductor package (semiconductor package) according to the prior art,
[2] 1B is a plan view showing an example of an internal view of a semiconductor package according to the prior art;
[3] Figure 1c is a cross-sectional view showing an example of the internal appearance of a semiconductor package according to the prior art,
[4] 2A is a plan view showing an example of an insulated tape applied to an embodiment of the present invention;
[5] 2b is a sectional view of FIG. 2a,
[6] 3A is a plan view illustrating an internal view of a semiconductor package according to a first embodiment of the present disclosure;
[7] 3B is a cross-sectional view illustrating an internal view of a semiconductor package according to a first embodiment of the present invention;
[8] 3C is an enlarged view of a portion P of FIG. 3B;
[9] 4A is a plan view illustrating an internal view of a semiconductor package according to a second embodiment of the present disclosure;
[10] 4B is a cross-sectional view illustrating an internal view of a semiconductor package according to a second embodiment of the present invention;
[11] 4C is an enlarged view of a portion L of FIG. 4B;
[12] FIG. 5a shows a dummy bar in which a middle portion is formed to be bent;
[13] Figure 5b is a view showing a dummy bar formed by separating the middle portion,
[14] FIG. 5C shows a dummy bar in which a middle portion is separated and the separated portions are formed to be offset from each other; FIG.
[15] FIG. 5D shows a dummy bar formed to be supported by a die pad. FIG.
[16] * Description of the drawing on the main parts of the drawing *
[17] 20: outer lead 40: inner lead
[18] 60: die pad 80: tie bar
[19] 100, 100a, 100b, 100c, 100d: dummy bar 140: bonding pad
[20] 120: semiconductor chip 210: package body
[21] 160: bonding wire 220, 240: conductive bonding means
[22] 260: insulating tape 262: insulating tape body
[23] 202a, 202b: internal lead groove 280: conductive plating layer
[24] 204a, 204b: bonding wire attachment groove
[25] 180: conductor circuit pattern
[30] In order to achieve the above object, the present invention provides a semiconductor chip including a plurality of bonding pads, a die pad on which a semiconductor chip is mounted, and bonding pads formed at a predetermined distance from the die pad and correspondingly bonded to the bonding pads. A semiconductor package comprising a plurality of internal leads connected to a plurality of internal leads and a die pad, the semiconductor package including a semiconductor chip, a die pad, internal leads, and a package body encapsulating the tie bars. A plurality of conductor circuit patterns, and inner lead attaching grooves and bonding wire attaching grooves each exposing the conductor circuit patterns, the dummy bars formed between the conductors, and exposed to the inner lead attaching grooves, respectively. Conductive adhesive means are formed in the circuit patterns, and the conductive circuit exposed to the bonding wire attachment grooves The furnace patterns include an insulating tape having a conductive plating layer formed thereon, wherein the insulating tape is attached from the dummy bars across the inner leads, the conductive bonding means is attached to the inner lead, and the conductive plating layer has a bonding wire bonded to the bonding pad. It provides a semiconductor package characterized in that the bonding.
[31] Hereinafter, a semiconductor package having an insulating tape including a conductor circuit pattern according to the present invention will be described in detail with reference to the accompanying drawings.
[32] 2A and 2B are a plan view and a cross-sectional view showing an example of an insulating tape 260 applied to an embodiment of the present invention. As shown in FIGS. 2A and 2B, the insulating tape 260 may be formed of, for example, an insulating tape body 262 formed of an insulating material such as polyimide, and an insulating tape body 262. The plurality of conductor circuit patterns 180 formed of a conductive material such as copper and the conductor circuit pattern 180 are exposed to the outside of the insulating tape body, and there for example conductive bonding means such as silver epoxy ( 240 is formed and the inner lead attaching grooves 202a to which the inner lead is attached, and the conductor circuit pattern 180 are exposed to the outside of the insulating tape body, where there is a conductive plating layer 280 such as, for example, silver plating. ) Is formed and is composed of bonding wire attachment grooves 204a to which a bonding wire is attached. Since the conductor circuit patterns 180 may be formed using a method such as etching, for example, the conductor circuit patterns 180 may be easily applied to a manufacturing method for mass production rather than directly processing the internal lead 40. And it can also form more finely. The position of the inner lead attaching grooves 202a and the bonding wire attaching grooves 204a may be changed depending on the configuration condition of the insulating tape.
[33] 3A and 3B are plan and cross-sectional views illustrating an internal view of a semiconductor package according to a first embodiment of the present invention, and FIG. 3C is an enlarged view of portion P of FIG. 3B. As shown in FIGS. 3A and 3B, the first embodiment forms dummy bars 100 between the die pad 60 and the inner leads 40, from the inner bars 40 from the dummy bars 100. The insulating tape 260 is configured to be attached to the insulating tape 260, and the insulating tape 260 is attached to the bottom surfaces of the dummy bars 100 and the inner leads 40. FIG. 3C is an enlarged view of a portion P of FIG. 3B, showing in detail the insulation tape 260 applied to the present embodiment is attached to the bottom surface of the dummy bar 100 and the inner lead 40. According to the present invention, the bonding wire attachment grooves 204a applied in the present embodiment are formed between the dummy bar 100 and the inner lead 40, and the conductive adhesion means 240 is formed in the inner lead attachment grooves 202a. The conductive plating layer 280 is formed in the grooves 204a having the bonding wires.
[34] 4A and 4B are plan and cross-sectional views illustrating an internal view of a semiconductor package according to a second exemplary embodiment of the present invention, and FIG. 4C is an enlarged view of portion L of FIG. 4B. As shown in Figs. 4A and 4B, in the second embodiment, the dummy bars 100 are formed between the die pad 60 and the inner leads, and the insulating tape is attached from the dummy bars 100 to the inner leads. The insulating tape 260 is attached to the upper surfaces of the dummy bars 100 and the inner leads 40. FIG. 4C is an enlarged view of the portion L of FIG. 4B, showing in detail the insulation tape 260 applied to the present embodiment is attached between the dummy bars 100 and the inner leads 40. In the inner lead attaching grooves 202b and the bonding wire attaching grooves 204b, the conductive bonding means 240 and the conductive plating layer 280 are formed as in the first embodiment, but the bonding wire attaching grooves applied in the present embodiment ( 204b) is formed within the range of the width of the dummy bars. Forming the bonding wire attachment grooves 204b within the range of the width of the dummy bars may have an effect of improving the performance of wire bonding during wire bonding.
[35] 5A to 5D are views showing the shape of the dummy bars 100a to 100d formed between the die pad 60 and the inner leads and for attaching the insulating tape according to the present invention. It is formed across the tie bar and the tie bar so as to be supported by the middle of the curved dummy bar (100a) in the middle, Figure 5b is formed across the tie bar and tie bar so as to be supported by the tie bars, 5C shows the shape of the separated dummy bars 100b, and FIG. 5C is formed between the tie bars and the tie bars so as to be supported by the tie bars, the middle of which is separated, and the arrangement of the separated dummy bars 100c is shifted from each other. The dummy bars 100c are shown, and FIG. 5D shows the dummy bars 100d formed to be supported by die pads rather than tie bars.
[36] In the above, embodiments of the insulating tape composed of one body and several types of dummy bars are shown, but the present invention is not limited to the embodiments described above. For example, the insulating tape separated into two or more bodies may be applied to the present invention, or if the dummy bars have any shape, the insulating tape may be attached to the present invention.
[37] According to the structure of the semiconductor package having an insulating tape containing a conductor circuit pattern according to the present invention as described above, the problem of fine processing of the internal leads to reduce the size of the internal leads, and the resulting poor quality such as internal lead vents Problems such as manufacturing cost increase due to the increase in the use of expensive bonding wires, which may occur due to the gap between the die pad and the inner leads, and poor quality due to the increase in the length of the bonding wire such as wire sagging and wire sweeping. While preventing the effect of increasing the density of the inner leads.

权利要求:
Claims (7)
[1" claim-type="Currently amended] A semiconductor chip having a plurality of bonding pads formed thereon;
A die pad having the semiconductor chip mounted thereon;
A plurality of inner leads formed spaced apart from the die pad by a predetermined interval and electrically connected to the bonding pads corresponding thereto;
Tie bars supporting said die pad; And
A package body encapsulating the semiconductor chip, the die pad, the inner leads and the tie bars;
In the semiconductor package comprising a,
Dummy bars formed between the die pad and the inner leads;
A plurality of conductor circuit patterns, inner lead attaching grooves and bonding wire attaching grooves exposing the conductor circuit patterns are formed, respectively, and conductive bonding means are formed in the conductor circuit patterns exposed to the inner lead attaching grooves, An insulating tape having a conductive plating layer formed on the conductive circuit patterns exposed to the bonding wire attachment grooves; More,
Wherein the insulating tape is attached from the dummy bars to the inner leads, the inner lead is attached to the conductive adhesive means, and a bonding wire bonded to the bonding pad is bonded to the conductive plating layer. .
[2" claim-type="Currently amended] The semiconductor package of claim 1, wherein the insulating tape is attached to lower surfaces of the inner leads and the dummy bars, and the bonding wire attachment grooves are formed between the inner leads and the dummy bars.
[3" claim-type="Currently amended] The semiconductor package according to claim 1, wherein the insulating tape is attached to the inner leads and the upper surfaces of the dummy bars, and the bonding wire attachment grooves are formed within a width of the dummy bars.
[4" claim-type="Currently amended] The semiconductor package of claim 1, wherein the dummy bars are formed between the tie bars and the tie bars so as to be supported by the tie bars, and the middle of the dummy bars is curved.
[5" claim-type="Currently amended] The semiconductor package of claim 1, wherein the dummy bars are formed across the tie bars and the tie bars so that the dummy bars are supported by the tie bars.
[6" claim-type="Currently amended] The method of claim 1, wherein the dummy bars are formed across the tie bars and the tie bars so as to be supported by the tie bars, and are formed so as to be separated from each other, wherein the positions of the separated dummy bars are shifted from each other. A semiconductor package characterized by the above-mentioned.
[7" claim-type="Currently amended] The semiconductor package of claim 1, wherein the dummy bars are formed to be supported by the die pad.

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同族专利:

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公开号 | 公开日

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引用文献:

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公开号 | 申请日 | 公开日 | 申请人 | 专利标题

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法律状态:
2001-06-27|Application filed by 삼성전자 주식회사

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2001-06-27|Priority to KR1020010036957A

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2003-01-06|Publication of KR20030000816A

优先权:

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申请号 | 申请日 | 专利标题

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KR1020010036957A|KR20030000816A|2001-06-27|2001-06-27|Semiconductor package having isolated tape which include conductor circuit patterns|